Random access memories, such as static random access memories (SRAMs) or dynamic random access memories (DRAMs), generally comprise a multiplicity of addresses for writing therein data. Data in the addresses may be accessed, for example, through data latches for performing operations, e.g., programming, on a memory cell array, e.g., a non-volatile memory cell array.
Reference is now made to FIG. 1, which illustrates a typical random access memory array 10 of the prior art (the illustrated example is SRAM). The memory array 10 has 8 rows and 8 columns and has a capacity of 64 bits or 8 bytes. Each bit can be read or written by selecting it with an appropriate row line and appropriate column line simultaneously. Selection of the appropriate row and column is done by means of row and column addresses, which are the binary values of the row and column numbers in the memory array 10. In the illustrated example of FIG. 1, three bits are enough for addressing each row and an additional three bits are enough for addressing each column (each row or column address being numbered from 0 to 7, i.e., binary 000 to 111). Thus, a common 6-bit address can read or write each of 64 bits in the memory array 10.
Access to the rows may be controlled by a row decoder 12, and access to the columns may be controlled by a column decoder 14. The row and column decoders 12 and 14 may convert 3-bit row addresses and 3-bit column addresses to a single row select and a single column select signal, respectively.
It is noted that the “memory word length” refers to the memory array row length in bits. The memory array capacity is defined by the number of memory rows. Each appropriate bit in every memory array row belongs to a memory array column.
The memory array 10 may be accessed with a byte-aligned access using an 8-bit resolution. For such an access, all column lines may be activated and one of the row lines may be activated, thereby selecting all the bits in that row. Thus, a 3-bit row address is sufficient for accessing the whole byte.
The traditional, prior art organization of an SRAM is fine for such byte-aligned accesses, wherein if all the column lines are activated only one row line is activated. There is no ambiguity of two different rows that are both selected.
However, the prior art memory array structure is not capable of performing a nonaligned memory access. A “nonaligned memory access” is defined as an access wherein at least two column lines and at least two row lines are activated at the same time. An example of a nonaligned memory access is a request to read the four most significant bits of the top byte and the four least significant bits of the byte below, in a single data transaction. Such an access is impossible with the memory array 10, because it requires activating a pair of row lines and all the column lines, which creates an ambiguity in the memory array electric scheme.